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16-Bit Latchup Protected Analog to Digital Converter
TABLE 1. 7809LP PIN DESCRIPTION
PIN 21 SYMBOL BUSY DESCRIPTION
7809LP
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversions are maintained in the output shift register. Latchup Protection Analog Supply. Latchup Protection Digital Supply.
22 23 24
PWRD LPVANA LPVDIG
TABLE 2. 7809LP ABSOLUTE MAXIMUM RATINGS
PARAMETER Analog Inputs SYMBOL R1IN R2IN R3IN CAP REF 1 MIN -25 -25 -25 VANA + 0.3 -0.3 ---40 -0.3 TSTG -65 MAX 25 25 25 AGND2 - 0.3 0.3 7 7 0.3 85 VDIG + 0.3 150 UNIT V V V V V V V V
C
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Ground Voltage Differences: DGND, AGND2 VANA VDIG VDIG to VANA Specified Performance Digital Inputs Storage Temperature 1. Indefinite short to AGND2, momentarily short to VANA.
V
C
TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Integral Linearity Error -40 to 85C Differential Linearity Error -40 to 85C No Missing Codes 2 Transition Noise
3
MIN ----15 -----
TYP -----1.3 -7
MAX 3 5 -2, 3 -1, 6 --0.6 0.6 --
UNIT LSB 1 LSB LSB Bits LSB % % ppm/ C
Full Scale Error 4,5 Full Scale Error 4,5 (using ext. 2.5000 Vref) Full Scale Error Drift
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Full Scale Error Drift (using ext. 2.5000 Vref) Bipolar Zero Error 4 Bipolar Zero Error Drift Unipolar Zero Error 4 -40 to 85C Unipolar Zero Error Drift Recovery to Rated Accuracy after Power Down (1 uF Capacitor to CAP) Power Supply Sensitivity (VDIG = VANA = VD) 4.75 V > VD < 5.2 V -40 to 85C 1. LSB stands for Least Significant Bit. One LSB is equal to 305 V. 2. Not tested. 3. Typical rms noise at worst case transitions and temperatures. 4. Measured with various fixed resistors. MIN ---------TYP 2 -2 --2 1 --MAX -10 -3 16 --8 32
7809LP
UNIT ppm/ C mV ppm/ C mV mV ppm/ C ms LSB LSB
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5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error.
TABLE 4. DELTA LIMITS
PARAMETER ICC VARIATION +/- 10%
TABLE 5. 7809LP DIGITAL INPUTS
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER VIL VIH IIL, IIH SUBGROUPS 1, 2, 3 MIN -0.3 2.0 -TYP ---MAX 0.8 VD + 0.3 10 UNIT V V A
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 6. 7809LP ANALOG INPUT AND THROUGHPUT SPEED
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Voltage Ranges Impedance Capacitance1 Conversion Time Complete Cycle (Acquire and Convert) Throughput Rate 2 1. Guarenteed by design. 2. Tested by application of signal. 1, 2, 3 9, 10, 11 9, 10, 11 9, 10, 11 ---100 SUBGROUPS MIN TYP MAX
7809LP
UNIT
10 V, 0 V to 5 V See Table 2. 35 7.6 ---8 10 -pF s s kHz
TABLE 7. 7809LP AC ACCURACY SPECIFICATIONS
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(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Spurious-Free Dynamic Range, fIN = 20 kHz 1 Total Harmonic Distortion, fIN = 20 kHz 1 Signal-to-Noise (Noise + Distortion) 1 fIN = 20 kHz -60 dB Input Signal-to-Noise 1, fIN = 20 kHz Full-Power Bandwidth 1,3 1. Guaranteed by design. 2. All specifications in dB are referred to a full-scale 10 V input. 3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB. 9, 10, 11 SUBGROUPS 4, 5, 6 4, 5, 6 4, 5, 6 83 -83 -88 30 88 250 ----dB kHz MIN 90 -TYP 100 -100 MAX --90 UNIT dB 2 dB dB
TABLE 8. 7809LP SAMPLING DYNAMICS
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Aperture Delay Aperture Jitter Transient Response FS Step Overvoltage Recovery 1 SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 --MIN -TYP 40 2 150 MAX ---UNIT ns us ns
Sufficient to meet AC specification
1. Recovers to specified performance after 2 X FS input overvoltage.
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 9. 7809LP REFERENCE
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Internal Reference Voltage Internal Reference Source Current (Must be ext. buffer) External Reference Voltage Range for Specified Linearity 1 External Reference Current Drain 1. Tested by application of signal. Ext. 2.5000V Ref CONDITIONS No Load MIN 2.48 -2.3 -TYP 2.5 1 2.5 -MAX 2.52 -2.7 100
7809LP
UNIT V A V A
TABLE 10. 7809LP DIGITAL OUTPUTS
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER Data Format Data Coding Pipeline Delay SUBGROUPS CONDITIONS MIN TYP MAX UNIT
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Serial 16-bits Binary Two's Complement or Straight Binary Conversion results only available after completed conversion 2.3 ----15 -10 0.4 -10 -MHz
Selectable for internal or external data clock Data Clock Internal (Output Only When 9, 10, 11 EXT/INT Low -Transmitting Data) EXT/INT High 0.1 External (Can Run Continually) VOL VOH Leakage Current 1 Output Capacitance 1 1. Not tested. 1, 2, 3 1, 2, 3 1, 2, 3 ISINK = 1.6 mA ISOURCE = 500 A High-Z State, VOUT = 0V to VDIG High-Z State -4 ---
V A pF
TABLE 11. 7809LP POWER SUPPLIES
(SPECIFIED PERFORMANCE -40 TO +85C) PARAMETER VDIG VANA IDIG IANA Power Dissipation PWRD LOW PWRD HIGH SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 VANA = VDIG = 5V fs = 100 kHz
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CONDITIONS Must be < VANA
MIN 4.75 4.75 -----
TYP 5 5 0.3 16 ---
MAX 5.25 5.25 --132 100
UNIT V V mA mA mW
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 12. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
SPECIFIC FUNCTION Initiate Conversion and Output Data using Internal Clock CS 1>0 R/C 0 BUSY 1 EXT/INT 0 DATACL K Output PWRD 0
7809LP
SB/BTC OPERATION x Initiates conversion "n". Data from conversion "n1" clocked out on DATA synchronized to 16 clock pulses output on DATACLK Initiates conversion "n". Data from conversion "n1" clocked out on DATA synchronized to 16 clock pulses output on DATACLK
0
1>0
1
0
Output
0
x
Initiate Conversion and Output Data using External Clock
1>0 0 1>0
0 1>0 1
1 1 1
1 1 1
Input Input Input
0 0 x
x x x
Initiates conversion "n" Initiates conversion "n" Outputs a pulse on SYNC followed by data from conversion "n" clocked out synchronized to external DATACLK. Outputs a pules on SYNC followed by data from conversion "n-1" clocked out synchronized to external DATACLK 1. Conversion "n" in process. Outputs a pulse on SYNC followed by data from conversion "n-1" clocked out synchronized to external DATACLK 1. Conversion "n" in process.
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1>0
1
0
1
Input
0
x
0
0>1
0
1
Input
0
x
Incorrect Conversions
0
0
0>1
x
x
0
x
CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition Analog circuitry powered. Conversion will be initiated without time for acquisition Analog circuitry disabled. Data from previous conversion maintained in output registers
Power Down
x
x
x
x
x
0
x
x
x
x
x
x
1
x
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 12. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
SPECIFIC FUNCTION Selecting Output Format CS x x R/C x x BUSY x x EXT/INT x x DATACL K x x PWRD x x
7809LP
SB/BTC OPERATION 0 3 1 Serial data is output in Binary Two's Complement format. Serial data is output in Straight Binary format.
1. See Figure 4 for constraints on previous data valid during conversion.
TABLE 13. 7809LP INPUT RANGE CONNECTION
ANALOG INPUT RANGE 10V 5V 3.3V 0V to 10V 0V to 5V 0V to 4V CONNECT R1IN VIA 200 CONNECT R2IN VIA 100
TO TO
CONNECT R3IN TO CAP CAP CAP AGND VIN VIN
IMPEDANCE 22.9 k 13.3 k 10.7 k 13.3k 10.0 k 10.7 k
VIN AGND VIN AGND AGND VIN
AGND VIN VIN VIN AGND AGND
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TABLE 14. 7809LP CONVERSION AND DATA TIMING
(TA = -40 C TO 85 C UNLESS OTHERWISE SPECIFIED) SYMBOL t1 t2 t3 t4 t5 t6 t7 t6 + t7 t8 t9 t10 t11 t12 DESCRIPTION Convert Pulse Width BUSY Delay BUSY LOW BUSY Delay after End of Conversion Aperture Delay Conversion Time Acquisition Time Throughput Time R/C Low to DATACLK Delay DATACLK Period Data Valid to DATACLK HIGH Delay Data Valid after DATACLK LOW Delay External DATACLK SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
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MIN 40 ---------20 100 100
TYP ---220 40 7.6 -9 450 440 75 125 --
MAX 6000 65 8 --8 2 10 ------
UNIT ns ns s ns ns s s s ns ns ns ns ns
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16-Bit Latchup Protected Analog to Digital Converter
TABLE 14. 7809LP CONVERSION AND DATA TIMING
(TA = -40 C TO 85 C UNLESS OTHERWISE SPECIFIED) SYMBOL t13 t14 t15 t16 t17 t18 t19 t20 DESCRIPTION External DATACLK HIGH External DATACLK LOW DATACLK HIGH Setup Time R/C to CS Setup Time SYNC Delay After DATACLK High Data Valid Delay CS to Rising Edge Delay Data Available after CS LOW SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 MIN 20 30 20 10 15 25 25 6 TYP --------MAX ---
7809LP
UNIT ns ns ns ns ns ns ns s
t12 + 5 -35 55 ---
TABLE 15. 7809LP CONVERSION DATA TIMING
DIGITAL OUTPUT BINARY TWO'S COMPLEMENT (SB/BTC LOW) BINARY CODE Full Scale Range Least Significant Bit (LSB) + Full Scale (FS - 1 LSB) Midscale One LSB Below Midscale -Full Scale 10 305 V 5 153 V 3.33V 102 V 0V to 10V 153 V 0V to 5V 0V to 4V 76 V 61 V 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 7FFF 0000 FFFF 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 FFFF 8000 7FFF HEX CODE STRAIGHT BINARY (SB/BTC HIGH) BINARY CODE HEX CODE
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DESCRIPTION
ANALOG INPUT
9.99969 4.99984 3.33323 9.99984 4.99992 3.99993 5V 7V 1V 7V 4V 8V 0V 0V 0V 5V 2.5V 2V
-305 V -153 V -102 V 4.99984 2.49992 1.99993 7V 4V 9V -10V -5V 3.33333 3V 0V 0V 0V
8000
0000
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 1. CONVERSION TIMING
7809LP
FIGURE 2. SERIAL DATA TIMING USING INTERNAL CLOCK (CS, EXT/INT AND TAG TIED LOW)
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FIGURE 3. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ AFTER CONVERSION
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
FIGURE 4. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ DURING CONVERSION
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 5. OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
7809LP
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 6. OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
7809LP
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16-Bit Latchup Protected Analog to Digital Converter
LPTTM Operation
7809LP
Latchup Protection Technology (LPTTM) automatically detects an increase in the supply current of the 7809LP converter due to a single event effect and internally cycles the power to the converter off, then on, which restores the steady state operation of the device. A simplified block diagram of the 7809LP circuitry is shown in Figure 7. The LPTTM circuitry consists of two power switch and current sensor blocks, an LPTTM controller block, a BIT current load block, and an active input protection block.
Figure 7. 7809LP Simplified Block Diagram
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The power switch/current sensor blocks sense the supply current drawn by the protected device on the analog and digital supply pins. When a threshold level is exceeded on either supply line, indicating single event induced latchup of the protected device, a signal is sent to the LPTTM controller block. The LPTTM controller then drives the power switches to an off state which removes the power supplies from the protected device. At the same time, a signal is sent to open the active input protection circuits and the LPSTATUS output pin is activated. After a period of time sufficient to clear the latchup, the LPTTM controller drives the power switches and input protection back to the on state restoring the operation of the protected device. The LPTBIT circuit is used during system test to electrically trigger the latchup function by drawing current through the power switch/current sensor blocks sufficient to trigger the LPTTM protection.
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
Differences Between the 7809LP and the ADS7809 Because the 7809LP uses the ADS7809 die to perform the analog to digital conversion function, its operation and performance is very similar to the ADS7809 packaged part from Burr-Brown. In general the operation and application will be the same for both parts. There are three primary differences: the operation of the supply pins, the operation of the additional LPBIT and LPSTATUS pins, and the operation of the I/O pins when a latchup is detected. The ADS7809 provides separate analog and digital supply pins, VANA and VDIG. These same supply pins on the 7809LPRP should be connected to the analog and digital supplies. There is no limit to the capacitance that can be connected to these pins in the system application. The 7809LP package also provides access to the ADS7809 die supply pins with the LPVANA and LPVDIG pins. The signal paths between the supply input pins and the respective die supply pins are low resistance during normal device operation. When an excessive supply current due to a single event latchup is sensed on either of the supply pins, the LPTTM circuit opens both paths to the die supply pins allowing the latchup condition to clear. The LPVANA and LPVDIG pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal locations for attaching supply decoupling capacitors. CAUTION: The LPVANA and LPVDIG pins must not be connected to the respective power supplies since this will defeat the LPTTM power switch and could result in permanent latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to these decoupling pins because the large capacitance will increase the recovery time of the 7809LP. Low ESR ceramic capacitors should be used with a maximum of .2 F per pin. The LPBIT input provides a means to electrically test the LPTTM circuit. A high level on the this pin causes a preset current to be drawn in addition to the normal device current through the analog and digital current sensors. If the high level is maintained for a sufficient duration, it will trigger the LPTTM circuit which will cycle the power to the protected device. If the LPBIT remains high, the LPTTM circuit will continuously cycle the supply voltages off then on. Driving this input with a 10 s high level pulse is sufficient duration to assure the LPTTM circuit cycles the power off then on one time only. A high level on the LPSTATUS output indicates that the LPTTM circuit has removed power from the protected device. The LPSTATUS returns low when the power is restored. LPSTATUS can be used to generate an input to the system data processor indicating that an LPTTM cycle has occurred and the protected device output accuracy may not be met until after the respective recovery time to the event. During the time that power is removed from the protected device, it is critical that external circuitry driving the device I/ O pins does not back-drive the device supply through input protection diodes or similar integrated structures. Backdriving of the supply through the device I/O pins could contribute to an extended or even a permanent latchup condition. For the ADS7809 testing has shown that for the normal signal range of operation on the analog input pins R1IN, R2IN, and R3IN, latchup will not be sustained. In order to prevent back-driving the supply from the digital I/O pins DATA, SYNC, TAG, R/C, CS, and PWRD, the 7809LP incorporates active input protection circuits. These circuits act as transmission gates in series with the digital inputs. During normal operation, these gates are on and present low resistance connections between the package input pins and the respective die pins. When the LPTTM circuit detects a latchup, these gates are switched off and present a high resistance path between the package inputs and the die inputs. The protected I/O pins are crow barred during the latchup. The bidirectional signal, DATACLK, is also protected by a transmission gate.
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
Dedicated digital outputs are not similarly protected since in most applications there will be no appreciable drive signal on these outputs to back-drive the pins. Pull up resistors on these outputs should be 10 K or greater to limit the back-drive current. Low on resistance, transmission gate circuits are also connected between the package pins and the die REF and CAP pins. These gates minimize the transient loading on the external filter capacitors required on these pins. This greatly reduces the single event recovery time of the 7809LP to full accuracy after an LPTTM cycle. During an LPTTM cycle, all outputs of the 7809LP are invalid and unpredictable until after the functional recovery time. After the functional recovery time, data conversions occur with a degraded accuracy until the full accuracy recovery time. A summary of the pin differences between the ADS7809 and the 7809LP is provided in the table below.
TABLE 15. ADS7809 AND 7809LP PIN DIFFERENCES
PIN NUMBER 1-10 ADS7809 Various 7809LPRP Various PIN DIFFERENCE DESCRIPTION Equivalent function to ADS7809 pins 1-10 respectively. Timing specifications change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry on ADS7809 die inputs. Equivalent function to ADS7809 pins 11-18 respectively. Timing specifications change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry on ADS7809 die inputs. A built in test function of latchup protection. A TTL high level pulse for > 5 microseconds duration on this input will trigger latchup protection of the device. This input shall be low during normal operation.
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15-22
Various
Various
11
--
LPBIT
12
--
LPSTATUS Latchup protection status output. This TTL level output is low during normal operation and goes high during a 10 s decision time period prior to power being removed. If the latch up current does not last at least 10 s then LPTSTATUS will go low (inactive) after the 10 s decision period without power being removed. When latchup protection is triggered, this output will go high for the duration of the time that power is removed from the protected device (50 s). All output except LPSTATUS are invalid during the time that power is removed from the ADS7809 die. This output foes low within 1 us of the power being re-applied to the protected device. Functional operation of the device is within ~25 s after the LPSTATUS output returns low with degraded accuracy due to the latchup filter circuitry. Full accuracy is restored ~5 ms later. This output can be used to inform the system processor of the latchup protection trigger and the subsequent degraded accuracy in the 7809LPRP output data. Output pull-up resistors should be 10k or larger on outputs. I/O pins must not be driven high while this signal is active. VANA VDIG LPVANA Equivalent function to ADS7809 pin 19. Analog Supply Input. Equivalent function to ADS7809 pin 20. Digital Supply Input. Latchup protected analog supply pin to the ADS7809 die. Decouple to analog ground with 0.1 F ceramic capacitor. Do not exceed 0.2 F. Do not connect to VDIG and/or VANA. Latchup protected digital supply pin to the ADS7809 die. Decouple to digital ground with 0.1 F ceramic capacitor. Do not exceed 0.2 F. Do not connect to VDIG and/ or VANA.
13 14 23
VANA VDIG --
24
--
LPVDIG
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
Testing the 7809LPRP Latchup Protection Circuitry The LPVANA and LPVDIG pins provide direct access to the 7809LP converter supply pins for attaching external decoupling capacitors to ground. These pins can also be used to test the LPTTM operation and threshold level by sinking a pulsed current load to ground as shown in the test circuit in Figure 8. The most accurate threshold current measurements are made with the ADS7809 in its lowest power state (PWRD = 5V). The LPTTM operation and device recovery times are most easily measured using the LPBIT input to trigger protection and recovery. Applying a 10 sec high duration TTL level to the LPBIT pin causes internal test currents sufficient to trigger the LPTTM circuit to be drawn through both the analog and digital supply sense circuits. LPTTM operating characteristics are summarized in Table 16 according to the timing diagram shown in Figure 9. During the time that the power is cycled, output signals and data from the 7809LP are invalid. The LPSTATUS signal high indicates that power is removed from the ADS7809 die. When this signal is low, power is applied to the ADS7809 die. The LPSTATUS signal is used to measure the supply recovery time. The supply recovery time interval starts when the supply current rises (causing LPSTATUS to go high) and ends when the LPSTATUS signal stabilizes low again.
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Within the functional recovery time interval (~25 sec after the LPTTM circuit reapplies power), the normal functional operation of the converter is restored with less than 5% full scale error. Additional settling time is then required to return to full accuracy operation. Recovery time intervals are defined which indicate the time to recover first to within 8 bit accuracy, then to within 12 bit accuracy, and finally to full 16 bit accuracy. These recovery times are primarily due to the single event and power cycling effects on the reference circuits and the settling times of their respective filter capacitors.
TABLE 16. 7809LP LPTTM OPERATING CHARACTERISTICS
PARAMETER Supply Threshold Current Protection Time Supply Recovery Time Functional Recovery Time 8-bit Accuracy Recovery Time Full Accuracy Recovery Time SYMBOL ITHR TPT TSR TFR T8R TFAR CONDITIONS PWRD = 5V LPBIT = 2.4V for 5 s LPBIT = 2.4V for 5 s LPBIT = 2.4V for 5 s LPBIT = 2.4V for 5 s LPBIT = 2.4V for 5 s TYP 75 10 50 TSR + 25 80 5 UNIT mA sec sec sec sec msec
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 8. 7809LP LPTTM TEST CIRCUIT
C4 GND .1UF C4
7809LP
U? R1 -7.5V 200 R2 R3 100 22.9K 1 2 3 4 5 6 7 8 9 10 11 12
GND
.1UF S1 24 23 22 21 20 19 18 17 16 15 14 13
+ C1 2.2UF
+ C2 2.2UF
R1IN LPVDIG AGND1 LPVANA R2IN PWRD R3IN BUSY CAP CS REF R/C AGND2 TAG SB/BTC DATA EXT/INT DATACLK DGND SYNC LPBIT VDIG LPSTATUS VANA 7809LPRP
DIGITAL CONTROL AND MONITORING D1 1N4149 D2 IS +5V Q1 2N2369A R3 PULSE GENERATOR 2 + C3 10UF 50 1N4149 20 USEC PULSEWIDTH 0V -VP
GND
GND GND
PULSE GENERATOR 1 5 USEC PULSEWIDTH RT/FT < 10 NS 2.4V .4V
GND GND
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 9. 7809LP LPTTM TIMING DIAGRAM
2.4V PULSE GENERATOR 1 LPBIT .4V
7809LP
0V PULSE GENERATOR 2 -VP CHARGE CURRENT INTO DECOUPLING CAPACITOR IS PEAK ITHR SUPPLY CURRENT (IS) IS (TYP) 0 TPT TSR 5V IS (TYP)
LPSTATUS 0V
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ALL OUTPUTS
OUTPUTS VALID
OUTPUTS INVALID
OUTPUTS VALID
FULL SCALE (F.S.)
<1/20 F.S.
FULL ACCURACY OUTPUT DATA ERROR
<1/256 F.S.
FULL <1/4096 F.S. ACCURACY
>-1/20 F.S.
- FULL SCALE TFR T8R T12R TFAR
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16-Bit Latchup Protected Analog to Digital Converter
FIGURE 10. SEL CROSS SECTION
7809LP
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FIGURE 11. SEU CROSS SECTION
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16-Bit Latchup Protected Analog to Digital Converter
7809LP
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24-PIN RAD-PAK(R) FLAT PACKAGE
SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.420 0.040 0.006 0.255 0.015 0.006 -0.900 -0.268 0.055 DIMENSION NOM 0.278 0.017 0.008 0.596 0.400 -0.270 0.065 0.050 BSC 0.430 0.045 0.014 24 0.045 0.006 -MAX 0.302 0.022 0.010 0.640 0.410 0.440 0.272 --
Note: All dimensions in inches
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16-Bit Latchup Protected Analog to Digital Converter
Important Notice:
7809LP
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.
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16-Bit Latchup Protected Analog to Digital Converter
Product Ordering Options
7809LP
Model Number 7809LP RP F X Feature Option Details
Screening Flow
Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40C, +25C, +85C) E = Engineering (testing @ +25C)
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Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK(R) package
Base Product Nomenclature
16-Bit Latchup Protected Analog to Digital Converter
1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.
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